Integrated circuit devices such as microprocessors and peripheral circuits typically operate in a synchronized fashion at very high speeds. For example, in systems including several kinds of integrated circuit devices, each device commonly operates in synchronization with a clock signal provided to the device. Thus, such a system often includes one or more circuits for generating clock signals synchronized to a reference clock signal, such as a phase-locked loop (PLL) circuit that generates an output clock signal having the same phase as an input reference clock signal using a voltage controlled oscillator.
In some applications, however, the use of such PLL circuits may be disadvantageous, as lags associated with control of the voltage controlled oscillator may cause such a PLL circuit to take a significant time to generate an output clock signal having the same phase as the reference clock signal. These control lags may also result in undesirably high power consumption.
The use of delay locked loop (DLL) circuits has been proposed to avoid such problems. A typically DLL circuit generates a delayed clock signal from a reference clock signal, with the delayed clock signal typically being used as a reference signal for operation of devices. A typically DLL circuit uses a phase comparator to compare the phase of the reference clock signal with that of the delayed clock signal, and feeds back the comparison result to a delay controller that varies the delay of the delayed clock signal.
Conventional DLL circuits typically use a phase comparator similar to that used in PLL circuits. However, using such a phase comparator may be disadvantageous for operation of a DLL circuit. The output clock signal produced by a PLL typically is not a signal delayed from a reference clock signal, but rather a signal produced by a voltage controlled oscillator. Consequently, at arbitrary times, the output clock signal produced by the voltage controlled oscillator of a PLL may be synchronous with a pulse of a reference clock signal.
In contrast, the DLL delays an input reference clock signal to generate a delay clock signal, which generally imposes causality constraints on the operation of the phase comparator. For example, a DLL circuit may malfunction if its phase comparator attempts to synchronize a kth pulse of the reference clock signal with a corresponding pulse of the delayed clock signal produced from the kth pulse of the reference clock signal, as the delay circuit of the DLL generally cannot sufficiently advance the delayed clock signal to provide synchronization.